The present invention relates to a technique to alleviate reflection of signals caused by discontinuity or mismatch of characteristic impedances in signal transmission lines and ringing induced thereby, and more particularly to a technique effective when applied to semiconductor integrated circuits, electronic devices, memory modules, and motherboards mounted with memory modules.
Due to the maximization of operation speed and the minimization of power and voltage levels in semiconductor devices, there is a trend that the amplitudes of signals transmitted between semiconductor devices are further reduced from those of TTL interfaces. This would increase the relative magnitude of impact from the effect of reflection occurred during signal transmission between semiconductor devices, resulting in increased likelihood of such semiconductor devices to miscomprehend the logic values of the transmitted signals. This would lead to the degradation in the operational reliability of semiconductor devices or electronic devices, which in turn, would be detrimental to the maximization of the operating speed of such semiconductor devices.
As one of the prior art technologies, there is one disclosed in Japanese Patent Laid-Open No. 10-41803/1998, which takes note of such impedance mismatch. The disclosure of which pays attention to the output impedance of a semiconductor device itself, which is one of the factors for impedance matching. That is, it is difficult to give uniformity to the output impedances of semiconductor devices due to process variability etc. Even if such uniformity could be achieved, there still is a possibility of the occurrence of mismatch due to the inductance components of packages or printed boards. Accordingly, the aforementioned disclosure relates to an invention which provides the controllability over the number of the final output stage transistors of an output circuit. There is also another known circuit which is disclosed as an output buffer in Japanese Patent Laid-Open No. 9-307419/1997.